Some current data processing systems have more than one type of electronic (non-magnetic) storage, such as main storage (MS) and expanded storage (ES), which are the fastest of the large storage media in the system. MS must contain the instructions and data currently being executed by the system. Typically the MS address has 24 or 31 bits in computers built according to the widely used S/370 architecture, and the maximum MS size is accordingly limited to 2 to the 24th power, or 2 to the 31st power, respectively. ES effectively expands the size of the fast electronic storage in the system well beyond the maximum MS size without changing the number of bits in the MS address fixed by the system architecture.
Previously, whenever the active data and programs in the system were about to exceed the limits of the MS of a machine, a supervisory control program (such as the IBM MVS/370 program) moved lesser-used pages of data out of MS to auxiliary storage on DASD to free up space in MS. DASD speed has greatly increased over the past years, but it has slow access time which is greatly exceeded by the much faster access time of electronic storage (such as that used in MS and ES).
A way that has been found to expand the computer electronic storage without eliminating its MS storage constraints is to provide expanded storage (ES), in which the same number of address bits used for MS can also be used to address ES.
ES can have a much larger capacity than MS even when ES is limited to the same number of address bits as are used to address MS. This is because the same number of address bits can be used to address a much larger unit in ES than in MS in which a byte or word is generally the addressable unit. Currently, a 4096 byte page is the ES unit. Thus, the same number of address bits can address an ES memory that is 4096 times larger than an MS memory.
However, a memory that is addressed in page units is limited in the type of processing for which it can be directly used, since most programs do their processing in byte units. For example, a page memory may be usable for sorting strings comprised of page units, but it cannot be used for ordinary arithmetic processing which is done in byte units.
ES cannot be used as an addressable target for processor instructions provided for normal users. Because of this, no storage key has been provided to control direct ES access by processor instructions available to all users.
The most commonly used function for a page unit memory (ES) is for parking page units of data that cannot be kept in MS due to lack of MS space. Then ES may be used as a software managed lookaside cache for MS, so that pages of data can be retrieved at a much higher speed than they can be retrieved from DASD (direct access device, e.g. disk or drum) when required in MS.
Virtual addressing allows an operating system to provide shared use of a single physical MS without endangering the security or integrity of the users. Addressing in the user program is virtual. One or more address spaces contain the instructions and data of the program, and the program is written as if the bytes, words, and pages of these address spaces are contiguous in storage. This provides both convenience in programming in such an environment and the ability to share the real storage among multiple users but still maintain system integrity. A mechanism is provided which translates a virtual address to a real address during the interpretation of an instruction by a processor. The interface between this mechanism, called Dynamic Address Translation (DAT), and the privileged supervisory control program is a set of system control tables which specify whether or not the virtual pages reside in MS at any particular time and, if so, in which page frames of MS they are. If a virtual page is "backed" in MS, it is called "valid". Otherwise, it is "invalid". Instructions that address valid pages are executed directly by the processor, using the operands from MS. When an invalid operand is encountered, the processor signals the supervisory control program by means of an interruption. The control program assigns an available page frame of MS to the required virtual page, retrieves the page from the page cache in ES or DASD units, updates the system control tables to reflect the now-valid status of the retrieved page, and requests processor reexecution of the interrupted instruction. This process is invisible to the non-privileged user program and does not affect its program steps. Because the system control tables are under control of the privileged supervisory control program, multiple users may safely share MS through virtual addressing. The DAT mechanism provides the necessary isolation between them.
In the IBM S/370 system, the system control tables are in two levels for efficiency of storage use and are called Segment Tables and Page Tables. Each Page Table Entry (PTE) describes the status of a virtual page: valid or invalid; and, if valid, the MS address at which it may be found, and an indication as to whether or not a processor is to allow store operations into that page.
A logical address in the current S/370 architecture is an MS virtual address or an MS real address. If the state of the DAT bit is 1 in the current PSW of the processor, the logical addresses of the operands in the instructions are MS virtual addresses, and if the DAT bit is 0 they are MS real addresses.
Also, the prior art of processing includes the use of non-privileged move (copy) instructions in the IBM S/370 architecture. All of these move instructions are restricted to moving (copying) variable numbers of bytes of data in MS, and none can move data between multiple storage media. For example, the Move Long (MVCL) instruction can move a variable number of bytes from one MS location to another MS location, which are specified in the instruction parameters as a source logical address and a destination logical address. If any addressed byte is not located in an allocated MS page, an exception occurs in the instruction's execution, the instruction's execution is suppressed, interruption signals are stored, and the privileged control program is entered to allocate the page having that addressed byte, or take other action as required by the stored signals. The suppressed instruction is reexecuted when processing returns to the interrupted program.
In prior art, movement of a part of a page, or of a large number of pages, of data from a source storage location to a destination storage location was accomplished by using an S/370 MVCL (move character long) instruction, or by using an S/370 MVC (move character) loop routine, for which both the source and the destination pages had to have valid addresses in MS, and have their data transferred into the pages in MS, before the instruction execution could start. Whenever any MVCL instruction specified a virtual page invalid in MS, the processor signalled the supervisory control program with a page-translation exception, which interrupted the program containing the MVCL instruction and invoked the control program which translated the virtual address, assigned a page frame in MS, and transferred the data into the MS page frame from DASD or ES in the storage hierarchy.
Accordingly, the control program responded to each MVCL page fault by:
1. Translating the faulting virtual address to obtain a PTE address. PA1 2. Assigning a page frame in MS for the faulting virtual page. PA1 3. Performing an I/O or PAGEIN operation to bring the page contents into the assigned MS page frame. PA1 4. Validating the PTE by setting its fields to reflect the existence of the page in MS.
Once both source page and destination page existed in MS for the MVCL instruction, it could perform its data transfer, which could be a data merge by replacing one or more bytes of data at any contiguous location in the destination page with data bytes copied from any contiguous location in the source page. Further, the copy/replace operation of the MVCL instruction could include any number of contiguous pages and parts of pages. As can be seen, up to three data transfer operations could be required: First, I/Oing data into page(s) at the source operand address. Second, I/Oing data into page(s) at the destination operand address. Third, transferring the data between the locations designated in the MVCL instruction which could be a part of one or more pages. (The subject invention avoids some of the data transfers required by these prior instructions when a full page of data is to be copied.)
Strict security requirements must be enforced in allowing the accessing of the pages of data on ES, since the pages transferred to ES from MS can be from any and all programs processing in MS, including privileged program data which can cause system failure if misused, and data of different problem programs each of which may have personal data to be kept private to itself.
Therefore, privileged (i.e. supervisory) state is required to use prior S/370 instructions that copied a page of data between MS and ES, which are the PAGEIN and PAGEOUT instructions; they are the subject of U.S. Pat. No. 4,476,524 to Brown et al entitled "Page Storage Control Methods and Means", assigned to the same assignee as the subject application. The prior PAGEIN and PAGEOUT instructions are not available for use by application programs, because they are constrained to supervisory state which restricts their use to system control programs, due to the security requirement that application programs not be allowed to directly access data on the ES medium. On the other hand, the subject invention provides an instruction for accessing ES that is usable by an application program while maintaining the required ES security. Further, the PAGEIN and PAGEOUT instructions can only use real addressing for accessing a source page and a destination page; while the subject invention can use virtual addressing. Also, the PAGEIN and PAGEOUT instructions are incapable of moving a page within one medium; they cannot move a page within MS or within ES as can the subject invention. And the PAGEIN and PAGEOUT instructions designate the storage media for each page copy operation by the operand locations in the instruction, while no storage media designation need be used for the subject invention although it may actually do a transfer between different media.
European patent application 0 214 870 (Yoshida et al, assigned to Fujitsu), and its corresponding Australian patent specification 564809 (Application number 62458/86) disclose an instruction for using logical addressing for transferring data elements between an extension memory (EM) and a main memory (MM). The operation code of this instruction designates the direction of transfer, and a different opcode is used for each transfer direction. The first operand (B1, D1) is dedicated to specifying a Main Memory logical address. The second operand (X2, B2, D2) is dedicated to specifying the Extended Memory logical address. The R1 operand specifies a variable number of elements to be transferred between EM and MM; any of its instructions can transfer a variable number of page units or non-page units. The operands in the instruction of this European patent are medium-dependent, while the operands are medium-independent in the instruction of the subject invention. The instructions in this patent do not use the virtual addressing as alleged, because actual virtual addressing does not require its user to specify the media being used, which are required for the operands of this patent's instructions along with having a different opcode for each different direction of data movement between different media. (In the subject invention, no media is required to be specified by any operand, and a specified user intent may not be granted in the instruction's execution. The instruction in the subject invention does not designate any direction of transfer between physical media, and uses the same opcode for all transfer directions. No variable number of data elements is specified, since one page is transferred by the instruction of the subject invention.)
Prior patent application (PO9-88-019) having Ser. No. 07/274,062 filed in the USA on Nov. 21, 1988 (and assigned to the same assignee as the subject application) discloses a supervisory program's window mapping service that initializes MS or ES pages in a virtual address space by mapping the pages to a portion of a linear data set on AS (auxiliary storage, i.e. DASD). This application allocates page frames in MS or ES, writes the allocated MS or ES addresses into the PTEs (page table entries) of the allocated page frames, locates the requested data in a linear data set on AS, and reads the AS data into the allocated pages in MS or ES to complete the process of initializing the pages that are being mapped to a desired part of the linear data set on AS. For an application program to use this supervisory program service, the application program must provide a program that specifies the mapping parameters, including the virtually addressed pages being mapped as well as the starting address on the AS data set. The operation of this prior art programming ends when the allocated pages are initialized to contain the data of the accessed window. When an operand in the window is found to be invalid in MS, the supervisory control program is invoked by interruptions and it must, using programming means, retrieve the required page from ES, update the mapping table to reflect validity of the page in MS, and request the processor to reexecute the instruction that caused the interruption. (On the other hand, the subject application is primarily concerned with handling pages after they have been initialized in MS or ES, so that the subject invention might be used after the process of application Ser. no. 07/274,062 has completed to copy some of the initialized pages in the same address space or to other address spaces regardless of whether they happen to be in MS or ES. Further, the subject invention does not require the user to specify each medium (MS or ES) being used. The invention optionally allows the user to express an intention of wanting MS as the destination page medium because it is expected that the page will be referenced by a subsequent instruction in the same program. But even when a user expresses an intention for MS, the supervisory control program can nevertheless refuse the user's intention and put the page in ES when indicated by system circumstances with the subject invention.)
Prior patent application (PO9-88-020) Ser. No. 07/274,239 filed Nov. 21, 1988 (and assigned to the same assignee as the subject application) discloses a novel type of address space called a NMDS (Non-MS Data Space, backed by ES only, or backed by ES and/or AS, but never backed by MS). (The NMDS is now called a hiperspace in the IBM MVS/ESA operating system.) The 07/274,239 application discloses program routines (which can only exist in a privileged operating system); only privileged programs are disclosed to move/copy a virtual-addressed page between an NMDS type of address space and a common type of address space (backed by MS, ES or AS and which contains both programs and data). The privileged program routines are: CREAD, CWRITE, SREAD, and SWRITE. Each of these privileged routines is comprised of plural instructions. Any of these privileged routines may be specified and invoked by a parameter-list routine placed in an application program. The parameter-list routine interrupts its application program by calling the privileged program containing these routines to execute the called routine, after which control is passed back to the calling application program. The ability of the 020 routines to directly access ES prevents them from being directly executed by a non-privileged application program. Furthermore the 07/274,239 privileged routines can only move a page between a NMDS and a program/data address space.
(Unlike the prior art, the subject application provides a non-privileged copy page instruction usable by both privileged and non-privileged programs (e.g. application programs) to perform a page copy in or between any type of address space(s), which may be backed in any media, including media with only privileged access such as ES and AS, and media with both privileged and non-privileged access such as MS. The token for any type of address space may be placed on any non-privileged user's access list for use by the invention. All security requirements for the privileged accesses are maintained without leaving the application program as long as the source page and destination page were previously allocated in one or more of the electronic storages. Unlike the prior art, the subject invention can copy pages from any type of virtual address space, including an NMDS, a data space or a program/data address space without requiring the user to know what medium backs the source page. And unlike the prior art, the subject invention can copy pages to any type of address space, including NMDS, a data space or a program/data address space without requiring the user to know what medium backs the destination page, although the invention also has the novel feature of allowing the user to express an intention of having MS as the destination medium without the user having control of the choice of the destination medium.)
The conventional cache-bypass used by IBM large systems does not prevent the CPU's cache from receiving data. The bypass merely sends data fetched from MS directly to the CPU's execution unit on a path that bypasses the cache in response to a cache miss, while also copying the same data in the cache. (The cache bypass of this invention does not copy into the cache any data fetched from MS or stored into MS when MS is not the destination medium, while this data is being sent to the execution unit in response to a cache miss on the copy operation.)